In U.S. Pat. No. 164,612, Kaplinsky describes a programmable flip-flop circuit which includes a master inverter latch and a slave inverter latch with a pass transistor connected to the input of the master inverter latch and a special driver circuit connected between the output of the master inverter latch and the input of the slave inverter latch. The pass transistor and driver circuit are responsive to control signals supplied by complementary clock signals CLKand CLK or by multiplexers that select either the clock signals or a fixed logic level, to open or close a conductive path to the inputs of the respective master and slave latches. The driver circuit includes first and second transistors connected in series between a first terminal input and the input to the slave inverter latch, as well as third and fourth transistors connected in series between a second terminal input and the input to the slave inverter latch. The gates of the first and third transistors are driven by the output of the master inverter latch, while the gates of the second and fourth transistors are driven by one of the aforementioned control signals. The two terminal inputs connect the first and third transistors either to fixed logic high or low voltage levels or to multiplexers that provide a programmable selection of these voltage levels. In one embodiment, the selection by the multiplexers at these terminal inputs includes a feedback signal from the output of the slave inverter latch, thereby providing a toggle flip-flop programming option. The special driver circuit thus allows the flip-flop circuit to be programmed to operate as a D-type flip-flop, toggle flip-flop, or latch, or even be transparent to a signal and be programmed to provide a selected output polarity.
In U.S. Pat. No. 5,295,174, Shimizu describes a shift register having a plurality (N) of latch circuits which are located on a like plurality of signal paths. An N-by-1 multiplexer, located at the outputs of the plural signal paths, is controlled by a clock so as to select the output of each latch circuit in sequence.
In U.S. Pat. No. 5,148,052, Yellamilli describes a data latching circuit that employs a multiplexer to select either a direct input signal on one signal path or a latched input signal on an alternate signal path for output.
An object of the present invention is to provide a macrocell circuit which can be configured to operate as a flip-flop or as a latch, or which can be transparent to a signal, and which has a programmable output polarity, without sacrificing operational speed, and which is comparatively simple in terms of the number of transistor elements.